Computer Engineering @ Michigan

Jayce Clarke

Hardware Developer @ IBM · Ex-SpaceX

Hardware/software systems builder working across FPGA/RTL, embedded systems, computer architecture, and production software.

View Systems I've BuiltGitHubResume

build log

BUILD LOG

[✓]out-of-order RISC-V processor
[✓]low-latency FPGA packet pipeline
[✓]industrial AI vision tooling @ P&G
[✓]production software @ SpaceX
[→]pre-silicon validation @ IBM

Featured systems

Hardware modules, packet paths, and production tools.

A focused set of projects across CPU microarchitecture, deterministic FPGA datapaths, embedded hardware/software integration, industrial vision, and operator-facing software.

CPU-CORE

Out-of-Order RISC-V Processor

Designed an N-way superscalar R10K-style RISC-V processor in SystemVerilog with register renaming, a reorder buffer, and speculative execution.

R10K-style microarchitecture
Load-Store Queue, Gshare branch prediction, instruction prefetching, and Early Tag Broadcast
Verified with Synopsys VCS and Verdi
Developed high-coverage testbenches for correctness
Achieved a 7.8 ns critical path
SystemVerilogComputer ArchitectureVCSVerdiRISC-V
PACKET-RTL

Low-Latency FPGA Market Data Pipeline

Architected and verified a 7-stage, 250 MHz FPGA-targeted HFT pipeline processing NYSE XDP order-based market data over 10G Ethernet.

250 MHz FPGA-targeted pipeline
NYSE XDP order-based market data over 10G Ethernet
Full order book maintenance via cuckoo hash table lookup
3-level top-of-book tracking across 500 symbols
64-bit AXI-Stream datapath validated with cocotb and a Python reference model
FPGARTLAXI-StreamNYSE XDPcocotbLow Latency
EMBEDDED

Embedded FPGA Gaming Console

Designed an FPGA-based gaming console with VGA output, STM32 integration, NES controller input, IR sensors, and a wireless glove.

VGA output supporting games including Galaga and Pong
UART, SPI, and I2C communication on STM32
Integrated NES controller, IR sensors, and wireless glove peripherals
FPGA interface for data processing and display control
Embedded SystemsSTM32FPGAVGAUARTSPII2C
VISION

Industrial AI Vision Tooling

Built Python-based computer vision tooling for industrial OCR, Data Matrix/barcode decoding, defect detection, and manufacturing automation during internships at Procter & Gamble.

OCR and Data Matrix/barcode pipelines for industrial label-reading workflows
3D camera evaluation for defect-detection accuracy and speed
Preprocessing tuned for varied lighting and surface conditions
Manufacturing test-stand data collection and analysis
PythonComputer VisionIndustrial AutomationAI
PRODUCTION

Production Software at SpaceX

Worked on Starshield production software involving scheduling/tasking workflows, authorization/access control, operator-facing tooling, and metrics/alerting.

Angular and .NET
Scheduling and tasking features for satellite workflows
Authentication and access-control logic for new user access paths
Angular UI features plus production metrics and alerting
Angular.NETC#Production Software

Experience timeline

Work that sits close to real systems.

From pre-silicon validation and embedded firmware to production software and manufacturing automation.

IBM

Entry Level Hardware Developer, Pre-Silicon Validation

Starting full-time on a design verification team focused on C++/Python-based validation.

SpaceX

Software Engineering Intern

Built production software for operational workflows, access control, and internal tooling.

Procter & Gamble

Engineering Intern

Worked on AI vision, OCR, Data Matrix decoding, and manufacturing automation.

Michigan Solar Car

Firmware/Microsystems

Worked with RTOS, STM32, HAL, and embedded communication protocols.

Technical stack

Tools grouped by the layer they touch.

Comfortable moving from RTL and buses to firmware, production code, and applied computer vision tooling.

Hardware / RTL

SystemVerilogVerilogFPGARTL DesignComputer ArchitectureAXI-StreamVCSVerdiQuartusModelSim

Embedded

CC++STM32RTOSUARTSPII2CHALOscilloscopes

Software

PythonC#.NETAngularTypeScriptGitLinux

AI / Vision

OpenCVOCRData Matrix decodingImage preprocessingEvent-based cameras

Builder DNA

The through-line: timing, constraints, and depth.

A portfolio shape for someone who likes understanding the full path from signal to software.

Low-level systems

I like working where software meets timing, hardware, and physical constraints.

Performance

I care about latency, throughput, correctness, and understanding what happens at the cycle level.

Hard problems

I'm drawn to systems most people avoid because they require crossing abstraction boundaries.

Contact

Let's build near the metal.

Open to work and collaborations around hardware/software systems, FPGA pipelines, embedded platforms, computer architecture, and production engineering.

jaycejc@umich.eduLinkedInGitHubResume